Host-computing systems, such as personal computers, typically operate as nodes on a communications network. Each node is capable of receiving data from the network and transmitting data to the network. Data is transferred over a network in groups or segments, wherein the organization and segmentation of data are dictated by a network operating system protocol, and many different protocols exist. In fact, data segments that correspond to different protocols can co-exist on the same communications network.
In order for a node to receive and transmit information packets, the node is equipped with a network peripheral. The network peripheral is responsible for transferring information packets between the communications network and the host system. For transmission, a processor unit in the host system constructs information packets in accordance with a network operating system protocol and passes them to the network peripheral. In reception, the processor unit retrieves and decodes packets received by the network peripheral. The processor unit performs many of its transmission and reception functions in response to instructions from an interrupt service routine associated with the network peripheral. When a received packet requires processing, an interrupt may be issued to the host system by the network peripheral. The interrupt has traditionally been issued after either all of the bytes in a packet or some fixed number of bytes in the packet have been received by the network peripheral.
FIG. 1 is a block diagram of an exemplary conventional network peripheral 10 that accesses the media of a network following a standard protocol, Ethernet (ANSI/IEEE 802.3). The network peripheral 10 provides an interface between a local bus of a computer, in particular a peripheral component interconnect (PCI) local bus, and an Ethernet network media. The peripheral 10 includes a PCI bus interface unit 16, a buffer memory 18, and a network interface 26. The PCI bus interface 16 may provide an interface with an external CPU or other host via the PCI local bus, and may include a PCI slave interface 16a, which allows other devices on the PCI bus to take the initiative in accessing the peripheral 10 (slave mode), and a direct memory access (DMA) interface 16b, which allows the peripheral 10 to read from and write to a memory on the PCI bus at the peripheral 10's own initiative (master mode). The PCI bus interface unit 16 has an interrupt request output INTA used for supplying the CPU or a host with an interrupt request signal. The network peripheral 10 produces the interrupt request signal to indicate that one or more status flags are set. The status flags may represent such events as reception of a packet, transmission of a packet, the occurrence of an error, or a user interrupt.
A Control and Register (CAR) block 17 contains registers that support interactions between the PCI bus interface 16 and other devices. The CAR block 17 has registers that can be read and written by other devices through the PCI bus interface 16. A decoder may be provided in the CAR block 17 to decode register settings and generate signals accordingly. For example, the CAR block 17 may comprise a command register that decodes commands from the CPU and sends command signals to other blocks of the network peripheral 10. The CAR block 17 also contains an interrupt management block that manages the signaling of interrupt events and the activation of the interrupt pin to send interrupts to the CPU. The interrupt management block includes interrupt registers, counters and timers for controlling interrupts. Further, the CAR block 17 generates reset signals supplied to all other blocks of the peripheral 10, and provides input/output control.
The memory portion 18 includes, for example, an SRAM implemented on the network peripheral chip 10. The SRAM 18 may be accessed under the control of a first in, first out (FIFO) control unit 22, or may be segmented into a receive portion 18a and a transmit portion 18b for receive and transmit paths, respectively. The network peripheral 10 also includes a buffer management unit 24 configured for managing DMA transfers via the DMA interface 16b. The buffer management unit 24 manages DMA transfers based on DMA descriptors in host memory that specify start address, length, etc. The buffer management unit 24 initiates a DMA read from system memory into the transmit buffer 18b by issuing an instruction to the DMA interface 16b. 
The network interface portion 26, which may be referred to as a media access control (MAC) core, supports various physical connections and protocols. The physical connections include a general purpose serial interface (GPSI) 28, a media independent interface (MII) 30 for connecting to an external physical transceiver (PHY), an external address detection interface (EADI) 32, an attachment unit interface (AUI) 34 having an encoder and decoder, and a twisted pair transceiver media attachment unit (MAU) 36. The network peripheral 10 also includes a network port manager 38 and an auto-negotiation portion 40. The network port manager 38 performs MII handshaking via the MII port 30 in accordance with the IEEE 802.3 protocols. The auto-negotiation portion 40 performs IEEE-compliant negotiation with a PHY link partner to exchange data indicating the speed of the link partner, and whether the link should be half-duplex or full-duplex.
It will be appreciated that data communication systems may employ a wide variety of algorithms, such as to effect secure data transmissions and/or reception. Such algorithms may, in turn, employ a number of routine operations, such as add rotate add operations. Improving the speed of such operations can enhance data throughput.